1. Field of the Invention
This invention is related to the field of memory controllers.
2. Description of the Related Art
Digital systems generally include a memory system formed from semiconductor memory devices such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM including low power versions (LPDDR, LPDDR2, etc.) SDRAM, etc. The memory system is volatile, retaining data when powered on but not when powered off, but also provides low latency access as compared to nonvolatile memories such as Flash memory, magnetic storage devices such as disk drives, or optical storage devices such a compact disk (CD), digital video disk (DVD), and BluRay drives.
The memory devices forming the memory system have a low level interface to read and write the memory according to memory device-specific protocols. The sources that generate memory operations typically communicate via a higher level interface such as a bus, a point-to-point packet interface, etc. The sources can be processors, peripheral devices such as input/output (I/O) devices, audio and video devices, etc. Generally, the memory operations include read memory operations to transfer data from the memory to the device and write memory operations to transfer data from the source to the memory. The term “transaction” may be used interchangeably with “memory operation” throughout this disclosure. Additionally, “read memory operations” may be more succinctly referred to herein as “read operations” or “reads”, and similarly “write memory operations” may be more succinctly referred to herein as “write operations” or “writes”.
Accordingly, a memory controller is typically included to receive the memory operations from the higher level interface and to control the memory devices to perform the received operations. The memory controller generally also includes queues to capture the memory operations, and can include circuitry to improve performance. For example, some memory controllers schedule read memory operations ahead of earlier write memory operations that affect different addresses.
In certain situations, as the amount of memory operations received by the memory controller increases, the latency experienced by the memory operations also increases. For real-time memory operations, increased latency may result in a significant degradation of performance.